发明名称 Method for manufacturing wafer-level fan-out package
摘要 Provided are a semiconductor package and a method for manufacturing a semiconductor package. The method for manufacturing a wafer-level fan-out package includes attaching semiconductor chips sawed to have a predetermined size to one surface of a wafer at predetermined intervals, forming a first passivation layer on surfaces of the semiconductor chips and the wafer, forming a redistribution layer electrically connected to the semiconductor chips on portions of an upper surface of the first passivation layer, forming a second passivation layer on the upper surface of the first passivation layer and surfaces of portions of the redistribution layer, forming external connection terminals on portions of the redistribution layer in which the second passivation layer has not been formed, and performing sawing along package boundary lines (sawing lines) and polishing the wafer to be removed such that lower surfaces of the semiconductor chips are exposed.
申请公布号 US9466586(B1) 申请公布日期 2016.10.11
申请号 US201514794185 申请日期 2015.07.08
申请人 STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD. 发明人 Choi Jai Kyoung;Kim Eun Dong;Jung Hyun Hak;Kim Hyeong Min;Lim Su Kyung
分类号 H01L23/00;H01L21/78;H01L21/027;H01L21/288;H01L21/768;H01L21/56 主分类号 H01L23/00
代理机构 代理人
主权项 1. A method for manufacturing a wafer-level fan-out package, the method comprising: attaching semiconductor chips sawed to have a predetermined size to one surface of a wafer at predetermined intervals; forming a first passivation layer on surfaces of the semiconductor chips and the wafer; forming a redistribution layer electrically connected to the semiconductor chips on portions of an upper surface of the first passivation layer; forming a second passivation layer on the upper surface of the first passivation layer and surfaces of portions of the redistribution layer; forming external connection terminals on portions of the redistribution layer in which the second passivation layer has not been formed; and performing sawing along package boundary lines and polishing the wafer to be removed such that lower surfaces of the semiconductor chips are exposed.
地址 KR