| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit which has high responsiveness, suppresses noise and is suitable for high-speed data communications. <P>SOLUTION: A frequency of an oscillated output from a variable oscillation circuit is divided by a frequency divider circuit, a pulse delayed just for one cycle of the oscillated output is generated from the output signal, and intermediate phase signals of a plurality of ways dividing a phase difference for the one cycle into a plurality of parts are formed by a phase mixing circuit. According to a prescribed control signal, one intermediate phase signal is selected by a selector circuit and compared with a reference clock signal by a phase comparator circuit, an oscillating operation of the variable oscillation circuit is controlled to match phases of the both, and a clock signal is generated. <P>COPYRIGHT: (C)2004,JPO |
