| 摘要 |
An array (30) of non-volatile floating gate memory cells arranged in a plurality of one or more rows and columns, a plurality of one or more of the cells electrically coupled to form a plurality of one or more pages (34), each of the cells having a first region, a spaced apart second region, a channel region between the first and second regions, a floating gate, and a control gate, comprises: a plurality of page-word lines (1,2,3,4), each page-word line connects to the control gate of one or more of the memory cells in one of the pages; a plurality of page-source lines(1,2), each page-source line connects to the second region of all of the memory cells in one of the pages; a plurality of bit lines (225-256), each bit line connects to the first region of all of the memory cells in one of the memory-cell-columns; a plurality of control circuits (40) arranged in rows and columns, each control circuit selectively couples signals to the page-word lines and the page-source lines of the pages; a plurality of control-circuit-row lines, each control- circuit-row line connects to all of the control circuits in a control-circuit-row, each control-circuit-row line enables the selective coupling in all of the control circuits in the control-circuit-row; a plurality of word lines (1-4,28-32), one or more of the word lines connect to all of the control circuits in each of the control-circuit-columns, the plurality of word lines are selectively coupled to the page-word lines by the control circuits; a plurality of source lines (1-2,14 -16) ,one or more of the source lines connect to all of the control circuits in each of the control-circuit-columns, the plurality of source lines are selectively coupled to the plurality of page-source lines by the control circuits. |
