发明名称 |
TECHNIQUE OF LESSENING GATE LEAKAGE IN SLEEP MODE TO APPLY INPUT PATTERN TO DEVICES |
摘要 |
PURPOSE: A technique is provided to lessen gate leakage in sleep mode by applying an input pattern to one or more out of a plurality of devices of a circuit. CONSTITUTION: An input pattern is applied to one or more out of the first plurality of devices of a circuit in sleep mode(401). By responding the application of the input pattern, a substantially identical voltage is generated at a source, gate and drain terminals of each of a majority of the first plurality of devices(402). At this time, gate leakage is lessened. The circuit is dynamic circuit.
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申请公布号 |
KR20040051497(A) |
申请公布日期 |
2004.06.18 |
申请号 |
KR20030078592 |
申请日期 |
2003.11.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALON ELAD;BURNS JEFFREY L.;NOWKA KEVIN J.;RAO RAHUL M. |
分类号 |
H01L21/822;H01L27/04;H03K19/00;(IPC1-7):H01L21/335 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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