| 发明名称 | Manufacturing method of semiconductor device and semiconductor device | ||
| 摘要 | A method of manufacturing a stacked semiconductor device having two or more wafers may include forming a conductor on an upper wafer, the conductor configured to electrically connect input terminals together that have no input protection circuit against ESD; forming front side micro-bumps on a front side of the upper wafer, the front side micro-bumps configured to electrically connect to back side micro-bumps on the upper wafer; forming a TSV structure, the TSV structure configured to facilitate electrical connections between the front and the back side of the upper wafer; forming back side micro-bumps on the back side of the upper wafer, the back side micro-bumps configured to electrically connect with front side micro-bumps on the lower wafer; stacking the upper wafer on the lower wafer; and separating the conductor such that each of the input terminals are electrically independent from other ones of the input terminals. | ||
| 申请公布号 | US9484387(B2) | 申请公布日期 | 2016.11.01 |
| 申请号 | US201314437445 | 申请日期 | 2013.10.22 |
| 申请人 | Shizukuishi Makoto | 发明人 | Shizukuishi Makoto |
| 分类号 | H01L27/14;H01L27/146;H01L27/02;H01L23/48;H01L23/60;H01L25/065;H01L25/00;H01L21/3213;H01L21/768;H01L21/82 | 主分类号 | H01L27/14 |
| 代理机构 | Harness, Dickey & Pierce, P.L.C. | 代理人 | Harness, Dickey & Pierce, P.L.C. |
| 主权项 | 1. A method of manufacturing a stacked semiconductor device including two or more wafers, the two or more wafers including at least an upper wafer and a lower wafer, the method comprising: forming active elements on the upper wafer; forming a conductor on a front side of the upper wafer, the conductor configured to electrically connect terminals including a ground and a power supply together with input terminals that have no input protection circuit, the input protection circuit being a circuit configured to absorb voltages resulting from electro-static discharge (ESD) events; forming front side micro-bumps on the front side of the upper wafer; forming a through silicon via (TSV) structure, the TSV structure configured to facilitate electrical connections between the front side and a back side of the upper wafer; forming back side micro-bumps on the back side of the upper wafer, the back side micro-bumps configured to electrically connect with the TSV structure and front side micro-bumps on a front side of the lower wafer; stacking the upper wafer on the lower wafer; and separating the conductor such that the input terminals are electrically independent from each other. | ||
| 地址 | Sendai JP | ||