Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code

摘要

A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

主权项

1. A computing device, comprising:
one or more processors configured to: receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
determine information associated with a permutation matrix for the LDPC code, the permutation matrix including a group of rows, each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code, the permutation matrix including a group of columns, each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and the permutation matrix including a set of values, each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
compute a parallelization factor associated with the permutation matrix, the parallelization factor being computed based on the set of values included in the permutation matrix;
determine, based on the parallelization factor, whether the permutation matrix satisfies the design threshold; andprovide information indicating whether the permutation matrix satisfies the design threshold, where the one or more processors, when computing the parallelization factor, are configured to: determine a group of column differences associated with the permutation matrix, each column difference, of the group of column differences, corresponding to a column of the group of columns, and being equal to a smallest difference between any two values included in the column; and identify the parallelization factor based on the group of column differences, the parallelization factor being equal to a smallest value included in the group of column differences.