Electroless metal through silicon via

摘要

A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 μm are provided on both sides of the wafer.

主权项

1. A semiconductor device comprising:
a substrate wafer of silicon; on oxide layer on the substrate; lateral redistribution/routing structures on the wafer surface; poly-silicon layers on the field and on the walls of the vias, respectively, a gap being present between said poly-silicon layers; a continuous Cu layer covering the lateral redistribution/routing structures and the surfaces in the via hole; a continuous barrier layer of Ni on which the Cu layer is provided, said barrier layer of Ni bridging the gap between the poly-silicon on the walls in the via and poly-silicon on the field, respectively, to provide a continuous conductive layer on which the Cu layer is provided.