发明名称 |
Synchronous semiconductor device, and inspection system and method for the same |
摘要 |
The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
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申请公布号 |
US6891393(B2) |
申请公布日期 |
2005.05.10 |
申请号 |
US20030373869 |
申请日期 |
2003.02.27 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUGAMOTO HIROYUKI;TANAKA HIDETOSHI;OGAWA YASUSHIGE |
分类号 |
G01R31/28;G01R31/317;G11C8/08;G11C11/401;G11C29/00;G11C29/06;G11C29/34;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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