发明名称 Semiconductor memory having hierarchical bit line structure
摘要 A first amplifier amplifies voltage of a first local bit line connected to static memory cells. Precharging circuits for precharging a first global bit line connected to an output of the first amplifier supply a precharging current through both ends of the first global bit line, respectively. Since the precharging current flows through the first global bit line in both directions, electromigration criteria can be made looser than in cases where the current flows in one direction. This makes it possible to avoid a defect which occurs due to electromigration of the first global bit line. Since the first global bit line can be reduced in wiring width, it is possible to minimize the layout area. As a result, the semiconductor memory can be reduced in chip size with a reduction in chip cost.
申请公布号 US6901017(B2) 申请公布日期 2005.05.31
申请号 US20030629809 申请日期 2003.07.30
申请人 FUJITSU LIMITED 发明人 SHIMIZU HIROSHI
分类号 G11C11/41;G11C7/12;G11C7/18;G11C11/417;G11C11/419;H01L21/8244;H01L27/10;H01L27/11;(IPC1-7):G11C7/00 主分类号 G11C11/41
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