发明名称 |
Shared bit line cross-point memory array incorporating P/N junctions |
摘要 |
A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.
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申请公布号 |
US6927430(B2) |
申请公布日期 |
2005.08.09 |
申请号 |
US20030404292 |
申请日期 |
2003.03.31 |
申请人 |
SHARP LABORATORIES OF AMERICA, INC. |
发明人 |
HSU SHENG TENG |
分类号 |
G11C7/00;G11C11/15;G11C11/56;G11C13/00;H01L27/24;(IPC1-7):H01L29/768 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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