| 摘要 |
<p>In a pipelined processor, when a conditional branch is effected in accordance with a state of calculation generated by immediately previous instruction, it is necessary for a conventional technique to insert a NOP (no operation) instruction before a conditional branch instruction. This lowers the processing efficiency. In order to solve this problem, a delay circuit generates a clock signal phi ' which is supplied to a program counter and an instruction memory. The clock signal phi ' is delayed behind a system clock phi . This obviates the need to insert such a NOP instruction and the processing efficiency is improved.</p> |
