发明名称
摘要 <p>A microcontroller includes a clock circuit with a register storing clock frequency information corresponding to a low speed or normal mode respectively operated by a low frequency or normal clock, which outputs a first signal according to a value set in the register when the low speed mode is designated during operation in the normal mode, a DRAM holding data, in the low speed mode, by operation in a self-refresh mode, and outputting a confirmation signal indicating switching to that mode, a DRAM circuit switching the DRAM to that mode based on the first signal, a ROM operated in the low speed mode, a remap circuit controlling an address circuit based on the confirmation signal, and outputting a second signal for switching a program execution address from the DRAM to an address of the ROM to control an address space in which a program is executed, the address circuit switching the address space based on the second signal.</p>
申请公布号 JP3699947(B2) 申请公布日期 2005.09.28
申请号 JP20020246566 申请日期 2002.08.27
申请人 发明人
分类号 G06F12/00;G06F1/04;G06F1/32;G06F12/02;G06F12/06;G06F15/78;(IPC1-7):G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址