| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a burden to a program for a dynamic reconfigurable processor. <P>SOLUTION: This dynamic reconfigurable processor 90 is provided with computing units 63, load units 61, store units 63, and delay units 62. The computing units 63 can switch input/output destinations and computing contents according to programmed configuration information arranged in M rows and N columns (M≥2, N≥1). The load units 61 arranged for the respective computing units 63 in a first row load data to be inputted to the computing units 63 from a local memory 40. The store units 63 arranged for the respective computing units 63 in the N-th row store data outputted from the computing units 63 into the local memory 40. The delay units 62 delay input of the data loaded by the load units 61 to the corresponding computing units 63 in the first row. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
