发明名称 Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device
摘要 A wiring substrate includes a first multi-layer wiring layer having a stacked via structure including a first electrode pad, a second multi-layer wiring layer having a non-stacked via structure including a second electrode pad. The second electrode pad is formed on an uppermost first insulating layer. The first electrode pad is formed on a second insulating layer which is located to a position lower by one layer than the first insulating layer, and the first electrode pad is arranged in an opening portion of the first insulating layer such that the upper face and the side face of the first electrode pad are exposed.
申请公布号 US9622347(B2) 申请公布日期 2017.04.11
申请号 US201414561540 申请日期 2014.12.05
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 Oi Kiyoshi;Kurihara Takashi
分类号 H05K1/18;H05K1/11;H05K3/46;H05K7/12;H05K7/00;H05K3/34 主分类号 H05K1/18
代理机构 Kratz, Quintos & Hanson, LLP 代理人 Kratz, Quintos & Hanson, LLP
主权项 1. A wiring substrate, comprising: a first multi-layer wiring layer having a stacked via structure including a first electrode pad, the stacked via structure including a via conductor having a tapered shape in which an upper diameter is larger than a lower diameter is stacked in a vertical direction; a second multi-layer wiring layer having a non-stacked via structure including a second electrode pad, wherein, the second electrode pad is formed on an uppermost first insulating layer, and an upper face and a side face of the second electrode pad are exposed from the first insulating layer; the first electrode pad is formed on a second insulating layer which is located to a position lower by one layer than the first insulating layer, and the first electrode pad is arranged in an opening portion of the first insulating layer and an upper face and a side face of the first electrode pad are exposed from the first insulating layer and the second insulating layer, and a solder is to be connected to the upper face and side face of first electrode pad and the upper face and side face of the second electrode pad.
地址 Nagano-shi JP