| 摘要 |
<p>1354717 Transistor bi-stable circuits WESTERN ELECTRIC CO Inc 7 Oct 1971 [12 Oct 1970] 46678/71 Heading H3T [Also in Division G4] Each bit 0-15 (Fig. 3, not shown) of a shift register consists of two cross.coupled NAND gates 101, 102, Fig. 1, and an inhibiting NAND gate 103 which enables the bi-stable to respond to SET inputs only when an ENABLE pulse occurs. The 0 and 1 outputs are normally 1 (high) and 0 (low) in the reset state, and only if the ENABLE input is low and a SET input simultaneously low can both transistors, Fig. 2B, of the gate combination 102, 103 turn off to allow the "1" output to go high. Information is parallel-transferred from for example register A to B. (Fig. 3, not shown) by clearing B with a reset signal to the gate 101 of each bit, and then enabling an output gate (303) in each bit of the A register to provide a SET input for the B register, and simultaneously enabling the enable gate 103 of each B register bit.</p> |
