发明名称 |
Antenna effect discharge circuit and manufacturing method |
摘要 |
An antenna effect discharge circuit is described for a device having patterned conductor layers, which may be exposed to charge inducing environments during a manufacturing process. The antenna effect discharge circuit has a terminal that is connected to a node on the device to be protected from charge accumulation and a gate, such as the gate of a field effect transistor in the circuit, and a terminal through which accumulated charge can be discharged to the substrate. A capacitor couples the gate in the antenna effect discharge circuit to the substrate. A voltage supply circuit is configured to provide voltage sufficient to bias the antenna effect discharge circuit in an off condition during operation of the device. A patterned conductor in the upper layer, and preferably the uppermost layer, of the device links the gate in the antenna effect discharge circuit to the voltage supply circuit. |
申请公布号 |
US9490249(B2) |
申请公布日期 |
2016.11.08 |
申请号 |
US201414265635 |
申请日期 |
2014.04.30 |
申请人 |
Macronix International Co., Ltd. |
发明人 |
Lue Hang-Ting;Yeh Teng-Hao |
分类号 |
H01L27/06;H01L27/02;H01L23/552;H01L21/8238;H01L27/115 |
主分类号 |
H01L27/06 |
代理机构 |
Haynes Beffel & Wolfeld LLP |
代理人 |
Haynes Beffel & Wolfeld LLP |
主权项 |
1. An integrated circuit device, comprising:
a substrate; a plurality of layers of patterned conductors and interlayer connectors on the substrate, the plurality of layers including an upper layer and one or more lower layers; an antenna effect discharge circuit on the substrate including a transistor having a gate, a channel well, and source and drain terminals in the channel well; a capacitor having a first terminal in, or connected to, the substrate, and a second terminal connected to the gate; a voltage supply circuit configured to provide a voltage sufficient to bias the antenna effect discharge circuit in an off condition during operation of the integrated circuit device; and a patterned conductor in the upper layer linking the gate to the voltage supply circuit and to the channel well of the transistor; and a switch configured to close during operation of the integrated circuit device, and having first and second terminals, the first terminal being connected to the gate by a first connector, and the second terminal being connected to the voltage supply circuit by a second connector, and wherein one or both of the first and second connectors includes the patterned conductor in the upper layer. |
地址 |
Hsinchu TW |