发明名称 SELF-TESTING CHECKING CIRCUIT
摘要 There is disclosed a self-testing checking circuit which checks that greater than or equal to k out of n input variables are 1. This circuit has the output (1,0) or (0,1) if the >/=k condition is satisfied and the output (0,0) or (1,1) if it is not. The circuit is self-testing, i.e., every line other than the primary inputs is tested during normal operation. The logical equation representing this circuit is (CK,N,D K,N) = (AN .EK,N-1(A1, A2, . . . ,A N-1),AN.E K-1,N-1(A1, A2, . . . ,A N-1)) WHEREIN A1 , . . . ,AN ARE THE N INPUT VARIABLES, EK,N,(A1, A2, . . . ,AN) DENOTES THE FUNCTION WITH THE THRESHOLD K, THE FUNCTION BEING 1 IF GREATER THAN OR EQUAL TO K OF THE N INPUT VARIABLES A1, A2, . . . ,A N ARE 1. It is suitably implemented as an OR circuit of (k) AND circuits, each of the latter AND circuits being a conjunct constituted by k of the n input variables. The function (ck,nd k,n) is a two-output threshold k function, i.e., it is (0,1) or (1,0) if greater than or equal to k out of the n input variable are 1 and (0,0) otherwise. Logical equations representing the two output k threshold function are CK,N= AN A1 A2 . . . AK VAN A1 A2 . . . AK-1 AK+1 V . . . VAN AN-K . . . AN-1 DK,N= AN A1 A2 . . . AK-1 V AN A1 A2 . . . AK-2 AK V . . . V AN AN-K+1 . . . AN-1 WHEREIN V REPRESENTS THE OR function.
申请公布号 US3784977(A) 申请公布日期 1974.01.08
申请号 USD3784977 申请日期 1972.06.20
申请人 IBM,US 发明人 CARTER W,US;WADIA A,US
分类号 G01R31/28;G06F11/08;G06F11/16;G06F11/22;H03M13/00;H04L1/24;(IPC1-7):G06F11/12 主分类号 G01R31/28
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