Low power and integrable on-chip architecture for low frequency PLL

摘要

An integrated circuit including a phase detector; a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current; and a dual input loop filter coupled to the first charge pump and the second charge pump.

主权项

1. An integrated circuit, comprising:
a phase detector; a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current, wherein the first charge pump and the second charge pump have synchronized outputs with respect to the inputs received from the phase detector; and a dual input loop filter coupled to the first charge pump and the second charge pump and comprising a first input receiving the low current and a second input receiving the high current and an output providing for an output voltage.