ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage

摘要

An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

主权项

1. A device, comprising:
at least one n-channel metal-oxide-semiconductor (MOS) transistor formed on a lightly doped p-substrate, including: a gate, a heavily doped n-drain region isolated from the gate and formed at least partially within an intermediately doped n-well region, wherein the intermediately doped n-well region is formed at least partially within a lightly doped deep n-well region, the intermediately doped n-well region including at least one vertical side edge and a bottom edge that are in direct contact with the lightly doped deep n-well region, wherein doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order, and a heavily doped n-source region; and a heavily doped p-collection region spaced apart from the heavily doped n-source region, wherein the heavily doped n-source region and the heavily doped p-collection region are formed at least partially within an intermediately doped p-well region.