STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER

摘要

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

主权项

1. A method of manufacturing a semiconductor device, the method comprising:
providing a first substrate comprising silicon; depositing epitaxially a silicon germanium (SixGe1-x) layer on an upper surface of the first substrate, the SixGe1-x layer having a higher concentration of germanium than the first substrate so that the SixGe1-x layer is in a state of in-plane biaxial compressive stress; providing a second semiconductor substrate having an insulating layer on one surface and attaching the second semiconductor substrate to the first substrate by a wafer bonding process so that the insulating layer is adjacent the SixGe1-x layer on the upper surface of the first substrate; removing a portion of the second substrate to leave a surface semiconductor layer on the insulating layer; etching through the surface semiconductor layer, the insulating layer and the stressed SixGe1-x layer, and into the first substrate in a pattern defined by a mask layer, thereby tensile straining the surface semiconductor layer across at least a portion of a lateral extent of the surface semiconductor layer between walls of one or more isolation trenches formed in the etching; and forming a semiconductor device having an active region in the surface semiconductor layer.