| 摘要 |
A digital logic network for implementing an edit function so that a field comprising a contiguous group of bits in a source register can be moved to a different location in a destination register without disturbing any of the other bits in the destination register, except those into which the field is transferred. A source register is coupled to a destination register by means of a shift matrix which also receives as a control input a shift count computed by subtracting the bit address in the source register of the first bit in the field to be relocated from the bit address of the first bit in the destination register where the field is to be moved. The bit address in the destination register of the first and last bits of the field to be moved are translated and used to enable gates disposed between the shift matrix output and the destination register such that only those gates associated with stages at or between the first and last bit address in the destination register will be fully enabled.
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