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经营范围
发明名称
SEQUENTIAL MEMORY
摘要
PURPOSE:While the address counter is not coinciding with the address register, the period of the clock pulse is shortened; and when coincidence is obtained, the pulse period is lengthened, thereby expediting the processing.
申请公布号
JPS5266344(A)
申请公布日期
1977.06.01
申请号
JP19750142552
申请日期
1975.11.29
申请人
TOKYO SHIBAURA ELECTRIC CO
发明人
YAMAZAKI GINZOU
分类号
G11C19/00;G11C19/28
主分类号
G11C19/00
代理机构
代理人
主权项
地址
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