| 摘要 |
<p>The phase-locked loop generates clock pulses synchronised with the passage through zero of an input data signal, e.G. for use in navigation systems. An A/D convertor continuously converts the input signal into a digital signal which is checked and stored by a memory when it receives a clock pulse. When a given digital signal count is reached an instruction sequence register reads out the count in synchronism with the zero passage of the input signal and generates a carry pulse at the end of the count. The carry pulse is fed to a pulse generator to produce a synchronous output clock pulse which leads or lags the zero passage of the input signal by the counting time of the instruction sequence register. A circuit feeds the output clock pulse to the memory which ensures this pulse and a second output clock pulse are synchronized with the zero passage of the input signal.</p> |
