| 摘要 |
1485569 Printed circuits SIEMENS AG 27 Aug 1975 [10 Sept 1974] 35275/75 Heading H1R In fabricating a multilayer wired substrate for a multistrip circuit a ceramic carrier 1 is perforated by a laser beam to form through holes 4, and both sides of the carrier are vapour coated in vacuo with a layer 5 of Ti overlain by a layer 6 of Au also extending to the walls of the holes. Photoresist layers 7, 8 not covering the holes are applied to the faces of the carrier, and covered by a mask which is exposed over the perimeter zones of the holes, developed, and removed; after which Au layers 9 are electrolysed on to the perimeters and hole walls. The photoresists are removed and the unreinforced parts of layer 6 and underlying layer 5 are etched out in successive solutions (Figs. 3, 4). Thereafter the ends of the holes at the lower face are sealed with Au paste under pressure over a silk screen template and heated to consolidate (Fig. 5, not shown), after which thick film wiring is impressed on the lower face 3 by silk screening on insulant layer 11 with square windows registering with the closed ends of holes 4, after which thick film wiring is silk screened on layer 11 to define alternate conductor path layers 12, 13, 14 and insulant layers 15, 16, 17 (Fig. 6); the assembly being subsequently heated to consolidate. Metal pins can be soldered into the wiring for external connections. A Ti base layer is then vapour deposited in vacuo on to the upper face 2 and overlain by vapour deposited Cu (Fig. 7, not shown) and a photoresist layer is applied to the face, exposed through a mask, and developed to present a negative image of a required thin film wiring structure. A layer 21 of Cu followed by a layer 22 of Ni are electrolytically deposited on the exposed areas of the Cu and Ti layers. The photoresist 20 is removed and a further photoresist layer 23 is applied (Figs. 8, 9) and exposed through a suitable mask and developed so that the thin film circuit structure is only covered at circular areas for later connection. A solder rejecting layer of Cr is deposited on the uncovered portions of the thin film wiring. The photoresist layer is removed, and the Cu and Ti layers are sequentially etched out from the areas not corresponding to the wiring. The connection surfaces not covered with Cr and the flanks of the wiring are electrolessly plated with gold at 25, 26, and layers 25 are dip coated with solder (which is not deposited in the Cr plated wiring surfaces and through hole walls) to produce dome contacts 28 for soldered connection of semi-conductor modules 27 (Fig. 10). |
