| 发明名称 | Sense amplifier circuit | ||
| 摘要 | A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistive device, a second resistive device, a fifth transistor and a sixth transistor. A gate of the first transistor is coupled to a drain of the fourth transistor. A drain of the first transistor is coupled to a gate of the fourth transistor. A gate of the second transistor is coupled to a drain of the third transistor. A drain of the second transistor is coupled to a gate of the third transistor. The first resistive device is coupled to a first data line and at least the drain of the first transistor or third transistor. The second resistive device is coupled to a second data line and at least the drain of the second transistor or the fourth transistor. The sources of the third and fourth transistor are coupled together. | ||
| 申请公布号 | US9466341(B2) | 申请公布日期 | 2016.10.11 |
| 申请号 | US201514820280 | 申请日期 | 2015.08.06 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFATURING COMPANY, LTD. | 发明人 | Hong Hyun-Sung |
| 分类号 | G11C7/00;G11C7/06;H03F3/16;G11C7/12;G11C11/4091;G11C11/4094 | 主分类号 | G11C7/00 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A sense amplifier circuit, comprising: a first transistor and a second transistor; a third transistor and a fourth transistor; a first resistive device; a second resistive device; a fifth transistor; and a sixth transistor; wherein a gate of the first transistor is coupled to a drain of the fourth transistor;a drain of the first transistor is coupled to a gate of the fourth transistor;a gate of the second transistor is coupled to a drain of the third transistor;a drain of the second transistor is coupled to a gate of the third transistor;the first resistive device is coupled to a first data line and at least the drain of the first transistor or the drain of the third transistor;the second resistive device is coupled to a second data line and at least the drain of the second transistor or the drain of the fourth transistor;a gate of the fifth transistor is coupled to the gate of the third transistor;a drain of the fifth transistor is coupled to the first data line;a gate of the sixth transistor is coupled to the gate of the fourth transistor;a drain of the sixth transistor is coupled to the second data line; anda source of the third transistor, a source of the fourth transistor, a source of the fifth transistor and a source of the sixth transistor are coupled together. | ||
| 地址 | TW | ||