| 摘要 |
A dynamic divider circuit for dividing a clock signal by n-1 where n is an odd integer is provided. The divider circuit includes n -series connected C-MOS inverter circuits, the output of the last of the series-connected inverter circuits being coupled to the input of the first of the series-connected inverter circuits to define a closed loop. n-1 inverter circuits include first switching circuits coupled thereto, the remaining inverter circuit having a second switching circuit coupled thereto, each of the switching circuits being adapted to receive the clock pulse to be divided and produce at the output of each of the C-MOS inverter circuits the divided clock signal.
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