| 摘要 |
1503944 Automatic exchange systems TELEFONAKTIEBOLAGET L M ERICSSON 5 June 1975 [10 June 1974 20 May 1975] 24335/75 Heading H4K A reed relay matrix includes a bi-stable electronic device in respect of each crosspoint for applying an operate and hold condition to its associated crosspoint relay, a command unit for initially applying a command signal to one row of the matrix, during which application, the current drawn through the row is measured to ensure that no relay is operative, a hold unit for subsequently applying an operate signal to one column of the matrix so as to operate the required crosspoint in conjunction with the still-applied command signal, a test unit for checking that one and only one relay has operated, and further means for applying a hold condition to the crosspoint if the check so permits. Fig. 2 depicts an 8Î8 relay matrix R11-R88 having a 4 layer bi-stable device H0-H7 associated with each crosspoint. In operation, a central control applies a matrix selection signal to CM, a row selection signal to YA0, YA1, YA2, and an operate/release signal to RLS. The signals are decoded and a particular row transistor, e.g. T8 is turned-on. The potential +E1 is thereby applied to the row. If no relay, e.g. R11-R18, is up, no current is drawn through RD and detector DE informs the control that so far all is well. Control then applies column selection signals to XM4-XM3 so that one of the bi-stables H0-H7 is triggered-on thereby permitting its associated relay to operate. The detector DE assesses the current drawn and informs control that all is well if the current is that required to operate one and only one relay. Thereafter control withdraws the command signals so that a transistor T11 turns-on to supply hold-current for the operated relay. In order to release the relay, control addresses the control circuit CU such that T11 is caused to turn-off whence, e.g. R11 and H0 restore. The circuit is such that temporary breaks in the hold path will not permit a relay to de-energize. Fig. 3 depicts the row control circuitry. Multiemitter transistors T5, T6 receive the decoded address and operate/release signals CM-RLS to thereby turn-on T8 or turn-off T11. Whilst T8 is on, T11 is off, the latter automatically coming-on for holding purposes when T8 is switched-off by central control (T 11 may be replaced by a 4 layer thyristor arrangement Fig. 4, not shown). The column control circuitry HC incorporates decoding transistors T1, T2 whose combined operation triggers a 4 layer device T4, T3, (this may be replaced by bipolar transistor Fig. 9, not shown) so as to permit the associated relay R11 to energize. Diodes D2, D3 and Zener diode DZ serve to temporarily hold the relay, should there be an intermittent break in the hold path transistors T 11, T3, T4, by virtue of the reverse p.d. induced in its coil during a change of current therein (also Fig. 10, not shown). Figs. 5, 6, 7 (none shown) depict arrangements of the individual column control circuits formed as a matrix of such circuits together with the decoding circuitry. The current detector (Fig. 8, not shown) may comprise three threshold circuits, a first operative immediately a command signal is applied if current is already flowing through an energized relay, a second operative if the current subsequently drawn corresponds to just one relay and a third indicative of more than one relay operative. An arrangement (Fig. 11, not shown) permits more than one row relay to operate due, e.g. to simultaneous markings, in order to apprise the central control of its mistake. Normally only one thyristor or transistor would operate (due to tolerances) if double marking occurs, so that one could not be sure if the operative relay is the desired one. |
