| 摘要 |
An interconnect assembly (38) for an embedded chip package includes a dielectric layer (42), first metal layer comprising upper contact pads (52, 54), second metal layer comprising lower contact pads (56, 58), and metalized connections (62) formed through the dielectric layer (42) and in contact with the upper and lower contact pads (52-58) to form electrical connections therebetween. A first surface of the upper contact pads (52, 54) is affixed to a top surface of the dielectric layer (42) and a first surface of the lower contact pads (56, 58) is affixed to a bottom surface of the dielectric layer (42). An input/output (I/O) of a first side of the interconnect assembly (38) is formed on a surface of the lower contact pads (56, 58) that is opposite the first surface of the lower contact pads (56, 58), and an I/O of a second side of the interconnect assembly (38) is formed on a surface of the upper contact pads (52, 54) that is opposite the first surface of the upper contact pads (52, 54). |
