| 摘要 |
A read only memory (ROM) structure in which a plurality of enhancement and depletion transistors are organized into a series-connected NAND logic matrix. The usual metal-to-diffusion contacts required for every one or two bits, as well as interweaved power supply lines required for every two row lines in conventional NOR logic circuits are not used in the series arrangement thereby minimizing the geometry of the ROM structure. In a preferred embodiment, logical information is stored within the ROM matrix by means of silicon gate metal oxide semiconductor field effect transistors which are arranged into a matrix having a number of common gate input rows and a number of series connected output columns which correspond to selected logic combinations of the inputs. The logical content of individual memory cells within the matrix is determined by providing either enhancement mode or depletion mode MOSFET transistors as elements of the matrix.
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