| 摘要 |
Oscillator pulses are coupled to a counter (2), the ultimate count interval of which causes an output amplifier (3) to produce a stimulating pulse and also to reset itself. A refractory control flip-flop (13) is also thereby reset, and blocks demand mode resetting pulses for the refractory period. A second counter (9) is resettable by the input amplifier, and defines a count interval during which noise pulses are rejected. A second flip-flop (11) is responsive to the second counter and to the refractory flip-flop selectively to reset the first counter based on demand pacing criteria.
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