Digital data transfer device - has control unit comprising clock coupled to random access instruction store and register

摘要

The device comprises a register and a decoder having its inputs coupled to a first output of the register. A transmitter state change acknowledgement signal generator comprises AND-gates, whose number is equal to that of transmitter message outputs. A priority transmitter operated interrupt signal generator and a random access instruction store are also provided. A switch has signal i/ps coupled to respective o/p buses and an enabling i/p coupled to a control unit. The control unit also includes a delay circuit.