发明名称 SEQUENCE CONTROLLER MONITOR
摘要 PURPOSE:To shorten fault repair by monitoring the test flag of the arithmetic processing section, storing the contents of the I/O element when they are satisfied, and externally displaying them only when they are related to their energization and deenergization. CONSTITUTION:When the operator checks the sources for which the specified output relay is not actuated, he assigns the above output relay address on the output address setting device 21. On the other hand, the sequence controller mainframe sequentially tests the input signal based on the program stored in memory 10. When the conditions of the input signal are satisfied, it assigns the address in the address register 26. When the address output instruction assigned on the output address setting device 21 is read, the comparator 24 generates output and displays the contents of the address register 26.
申请公布号 JPS54102476(A) 申请公布日期 1979.08.11
申请号 JP19780008651 申请日期 1978.01.27
申请人 发明人
分类号 G05B23/02;G05B15/02;G05B19/02;G05B19/048;G05B19/05 主分类号 G05B23/02
代理机构 代理人
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