发明名称 MICROPROGRAM FETCH PROCESS SYSTEM
摘要 PURPOSE:To enhance the reliablity of the system by providing the head address memory to the control memory in case the given machine order is executed and then providing the branch order to the address information in correspondence to the machine order along with operation of the high-speed exclusive memory. CONSTITUTION:When a certain machine order is set to machine order register 1, an access is given to head address storing memory 3 via the operation code 2 of the order for the high-speed exclusive memory. The address information on control memory 5 including head microorder 7 is stored in the address corresponding to the machine order of memory 3. In case some fault occurs in memory 3, code 2 is set to control memory address counter 4, and memory 5 is made access based on the contents of counter 4. Branch order 8 is stored in the address corresponding to the machine order of memory 5, and order 8 is read to be set to microorder register 6. The storing address of order 7 is indicated by the branch address written into the branch order, and order 7 is set to register 6 to carry out the machine order.
申请公布号 JPS5553746(A) 申请公布日期 1980.04.19
申请号 JP19780128280 申请日期 1978.10.18
申请人 FUJITSU LTD 发明人 MARUYAMA MITSUYUKI
分类号 G06F9/22;G06F9/26;G06F11/00 主分类号 G06F9/22
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