Execution unit for data processor using segmented bus structure.

摘要

A data processor having a novel execution unit (16) is disclosed which employs a segmented bus structure (10, 20, 32; 12, 22, 34) and a dual port register cell (138) in order to increase circuit density and in orderto allow address and data computations to occur simultaneously. The disclosed circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits.