Universal serializer architecture

摘要

Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip-flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.

主权项

1. A transceiver, comprising:
a first plurality of data flip-flops coupled to a data lookup circuit of a Serializer-Deserializer (SerDes) interface, wherein, during a clock cycle, a first one of the first plurality of data flip-flops is configured to receive a first bit of data stored in the data lookup circuit, and wherein the remaining ones of the first plurality of data flip-flops are configured to receive voltage information about the first bit of data; a second plurality of data flip-flops coupled to the data lookup circuit, wherein, during the clock cycle, a first one of the second plurality of data flip-flops is configured to receive a second bit of data stored in the data lookup circuit, and wherein the remaining ones of the second plurality of data flip-flops are configured to receive voltage information about the second bit of data; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.