Addressing circuit for store in telephone system - has decoder selecting several memory modules simultaneously during testing to reduce test time

摘要

The addressing circuit has a decoder (Q) decoding the incoming addresses for the column lines (1-8) of the store. The store consists of orthogonal column and row lines with memory modules (Sa) at their cross-points. The decoder executes different functions during testing and normal operation. In normal operation, the decoder selects a memory module. In the test mode, the decoder selects several memory modules simultaneously via several column lines in order to keep the time required for testing as short as possible. The decoder is therefore best realised as a memory itself and responding to control words.