| 摘要 |
PURPOSE:To supply correct switching signal and to prevent malfunction, by counting the clock pulse from the latch execution signal externally and supplying the frequency divider output as the timing signal for the latch circuit. CONSTITUTION:The execution signal S2 from a terminal 5 is taken as the reset input of the counter 7, and the clock pulse S1 from an oscillation circuit 4 is frequency-divided, and the frequency dividing output S3' is fed to the latch circuit 3 as the timing signal of latch. Accordingly, even if the phase of the clock pulse S1 and the latch execution signal S2 is closed together, for example, if the latch is made at the trailing of the counter output S3', the timing of latch is delayed by almost one clock period from the latch execution signal S2, avoiding malfunction. |
