发明名称 PSEUDO ERROR TRANSMISSION SYSTEM
摘要 PURPOSE:To make it possible to write error contents in a short time by externally setting the error contents without using a channel device and by generating a pseudo error when reading a pseudo external memory device. CONSTITUTION:Assuming that correct data would be written in pseudo disk device 1, central processor CPU transfers an error occurrence address and error data to error address registers R3 and R3' and error data register R2 by service processor SVP. Next, central processor CPU sends a read instruction and pseudo disk device 1 reads and sends correct data from IC memory 3. However, an address comparing circuit compares the address of register R3 with that of counter AC to find coincident timing and error data in register R2 is sent out of control part 4 as a substitute for the readout output of IC memory 3.
申请公布号 JPS5688550(A) 申请公布日期 1981.07.18
申请号 JP19790166531 申请日期 1979.12.21
申请人 FUJITSU LTD 发明人 ADACHI YUUTA
分类号 G06F3/06;G06F11/22;G06F13/00;G11B5/09;G11B20/18 主分类号 G06F3/06
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