| 摘要 |
PURPOSE:To enable a carry signal to be surely transmitted by outputting ligic 1 for charging of a carry line CL circuit which is operated by the output signal of the 1st half adder from a full adder consisting of said CL circuit and the 2nd half adder. CONSTITUTION:A CL circuit 36 is operated by the output of the 1st half adder HA 1 which has two output terminals, input terminals 3a, 3b. The 2nd half adder 44 is connected to the circuit 36 and these constitute a full adder. Said full adders are provided in parallel by the bit number of multiplicand. The output terminals 4b of these full adders are so constituted as to output logic 1 at the timing of charging the circuit 36. The addition signal of the circuit HA1 of the lowermost bit is held at logic 1, and the carry line operates normally without competing with the carry signal of the lowermost bit; therefore, the multiplying operation takes place accurately. |
