| 摘要 |
PURPOSE:To enhance transmitting efficiency and secure the data quality, by inserting a dummy bit only to the frame where the inhibited fixed pattern is generated in a PCM transmission system. CONSTITUTION:In response to the control signal, the multiplexer 6 supplies both the frame bit Fn and the dummy display bit Xn to the memory 8. When the bits Fn and Xn are read out successively out of the memory 8, the display pulse (d) is supplied to the dummy display bit circuit 12 from the suppressing pulse generating circuit 16 in accordance with the detection 15 of a fixed pattern. Then an alteration is given to the read-out bit Xn. The suppressing pulse (f) is supplied to the dummy inserting circuit 11 when the prescribed data bit is read out, and the dummy data bit is inserted in place of the prescribed data bit. The dummy display bit in the input signal is detected 22 at the receiving part, and the display bit is separated 24 from the dummy bit. |
