| 摘要 |
Disclosed is a bubble memory system that includes a plurality of bubble memory chips. Each of the chips have a number of minor loops, but only a predetermined portion of the loops are utilized to store information therein. The remaining loops may be defective and are not used. Data words that are to be stored in the bubble memory chips are passed through a first FIFO circuit which scrambles the bits in the words prior to their storage in the bubble memory chips. Due to this scrambling operation, no bits are stored in the defective loops. Data bits that are received from the bubble memory chips are passed thorugh a second FIFO circuit. There, all of the bits of each word are then realigned and presented at the FIFO output in parallel.
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