发明名称 CLOCK SELECTION SYSTEM
摘要 PURPOSE:To decrease the probability of data read-in error production by sampling the data signal at the rise and fall of a clock signal, in a system sampling in the same frequency as that of the data signal. CONSTITUTION:In a receiver for a digital communication, the discrimination as to if the fall changing point and rise changing point of a clock signal S4 are superimposed on an uncertain area of a data signal S1 or not, is performed at phase comparators 3, 4. If the changing point of the clock signal S4 is superimposed on the uncertain area of the data signal S1, the data signal S1 is sampled with the fall or rise of the clock signal S4. Thus, the sampling of the uncertain area of the data signal S1 is avoided, allowing to decrease the probability of data read-in error production.
申请公布号 JPS5748841(A) 申请公布日期 1982.03.20
申请号 JP19800123428 申请日期 1980.09.08
申请人 FUJITSU KK 发明人 OOHATA MICHINOBU;KAJIWARA MASANORI;FURUKAWA TAKAHIRO;MIZUSHIMA KOUJI
分类号 H04L25/40;H04L7/02;H04L7/033;H04L7/04 主分类号 H04L25/40
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