| 摘要 |
PURPOSE:To speed the whole processing by decreasing the amount of hardware of a vector processor by performing all of an instruction fetch, interruption recetion, etc., by a main processor and by executing vector instruction as succeeding group units by the vector processor. CONSTITUTION:A main storage device fetches instructions from a storage device 3 and, while storing them in an instruction buffer 4 temporarily, decodes instructions in the buffer 4 by the 2nd control circuit 8. As a result, when a scaler instruction is obtained, a scaler arithmetic device 6 is actuated to perform arithmetic. On the other hand, a vector instruction is obtained as a result of the decoding, the vector instruction is sent to a vector processor 2 through the 1st control circuit 7. Further, the circuit 8, when detecting a scalar instruction frollowing succeeding vector instructions, sends a final instruction signal, showing the ending of the succeeding vector instructions, to the processor 2. |
