ANALOG SWITCH HAVING REDUCED GATE-INDUCED DRAIN LEAKAGE

摘要

In an example, an apparatus includes an analog switch (102) having an n-type metal oxide semiconductor (NMOS) circuit (202) in parallel with a p-type metal oxide semiconductor (PMOS) circuit (204) between a switch input and a switch output. The analog switch (102) is responsive to an enable signal that determines switch state thereof. The NMOS circuit (202) includes a switch N- channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N- channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit (204) including a switch P-channel transistor coupled to a buffer P- channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit (208) is coupled to the analog switch (102) to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.