| 摘要 |
PURPOSE:To detect the first faulty module, by inputting outputs of respective check latch circuits of plural logic modules to latch circuits where these outputs are stored at every timing and stopping the latch timing by outputs of these latch circuits. CONSTITUTION:Outputs of respective check latches 2-6 of plural modules (Md) 1a-1n are operated for OR by an OR circuit 7 and are taken out. Signals 8a- 8n taken out from modules 1a-1n are connected to an Md detecting circuit 9, and are connected to latches 11a1-11a4 different in timing for every Md unit. Outputs of latches 11a1-11a4 pass through an OR circuit 12a, and NOR between the OR output of them and OR outputs of other Mds is operated in a circuit 13 and is connected to AND circuits 10a-10d. Timings T0-T3 are connected to circuits 10a-10d, and outputs of circuits 10a-10d are connected to trigger inputs of all latches. When the signal propagation time from a check latch to a latch is set as 1 timing, a corresponding latch is set to suppress updating of latches hereafter if the output is issued to some check latch, thus detecting a faulty Md. |
