| 摘要 |
A phase comparison circuit for producing an output signal which is a measure of the phase difference between first (A) and second (B) pulse trains applied to respective first and second inputs thereof. The circuit is immune to the omission of a pulse from one of the trains and to pulse length inequality in the two trains. It comprises a logic circuit, two switchable current sources connected to a capacitor (17), a switchable constant voltage source, i.e. a controllable switch (18) connected to the capacitor, and a sampling circuit connected to the capacitor. The logic circuit generates four output signals that control the first current source, the second current source, the constant voltage source, and the sampling circuit respectively so that the charge on the capacitor is changed in a positive sense by the first current source when a pulse of the first train is present while a pulse of the second train is absent and in the other sense by the second current source when a pulse of the second train is present while a pulse of the first train is absent. The capacitor charge is restored to a reference value (zero) by the constant voltage source when pulses of both trains are absent simultaneously. The sampling circuit samples the capacitor voltage when pulses of both trains are present simultaneously.
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