发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To always perform an operation with suited internal constitution and to increase the processing speed, by varying the connection among one or plural registers, an arithmetic unit and a data bus based on a program instruction. CONSTITUTION:The signal of a signal line 10 which indicates the connection at a connection controlling part is decoded by a decoder 41 by an instruction of a program. The value of output signals 301-436 are set at 0 or 1. This output signal line controls the intersections 101-236 among the input signals lines 8- 31 and the output signal lines 8-24 of a data bus, an arithmetic unit and a register. In such constitution, the combination among the register, arithmetic unit and data bus can be varied in various ways for each desired operation.
申请公布号 JPS5894035(A) 申请公布日期 1983.06.04
申请号 JP19810192640 申请日期 1981.11.30
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 TOKUNAGA YASUSHI
分类号 G06F7/00;G06F9/30;G06F9/318;G06F9/38;G06F17/10 主分类号 G06F7/00
代理机构 代理人
主权项
地址