Semiconductor integrated circuit and wiring method

摘要

PCT No. PCT/JP80/00025 Sec. 371 Date Oct. 27, 1980 Sec. 102(e) Date Oct. 15, 1980 PCT Filed Feb. 22, 1980 PCT Pub. No. WO80/01859 PCT Pub. Date Sep. 4, 1980.A large scale semiconductor integrated circuit and its wiring method employing a grid system where the layout space is partitioned in the form of a grid by vertical and horizontal line group having an interval larger than a length corresponding to a minimum dimension for a patterning in a manufacturing process; wiring patterns for making connection between each cell which is a unit of layout are depicted on such vertical and horizontal lines; and wirings are made on the basis of the wiring patterns. An interval (d) of these vertical and horizontal lines of the grid is the greatest common factor of the minimum wiring pitches of several overlapped wiring layers and is selected to a dimension which is smaller than said wiring pitch; and the vertical and horizontal line patterns are depicted on the vertical and horizontal lines having the same interval. The vertical and horizontal dimensions of the cell are an integer multiple of the interval (d) of the grid and cell terminals are disposed in an allowable wiring locations on the grid.