FIFO Register with independent clocking means

摘要

There is described a register circuit which is utilized with a system having the capability of interfacing between two data processing units which may have different operating speeds or data rate handling capabilities. The register permits writing and reading of data in a manner which is independent of the operating speed of the processing unit. The register provides pointers which selectively permit reading and/or writing in a prescribed manner but, at the same time, prevents writing or reading in a forbidden condition (i.e., writing in a full register or reading from an empty register).