Circuit arrangement having a plurality of series-connected shift registers

摘要

In the case of long shift register chains having a plurality of series-connected shift registers, the problem can occur that the data edge runs faster to the input of the respectively following shift register than the clock pulse edge, with the result that data signals can be lost. This problem is solved by the present invention by the clock signals (T) being inverted for successive shift registers (SR1, SR2, SR3). Every second shift register (SR2) has an additional stage (S25). Main fields of application of the invention are airport passenger information systems or large displays. <IMAGE>